High-Level Test Generation using Physically-Induced Faults - VLSI Test Symposium, 1995. Proceedings., 13th IEEE
نویسندگان
چکیده
A high-level fault modeling and testing philosophy is proposed which is aimed at ensuring,full detection of lowlevel, physical faults, as well as the industry-standard single stuck-line (SSL) faults. A set of independent functional faults and the corresponding ,functional tests are derived (induced) from the circuit under test; ofparticulur interest are SSL-induced functional faults or SIFs. We present, ,for the.first time, complete functional circuit models and tests for representative 74X-series and ISCAS-85 benchmark circuits, and apply the proposed methodology to them. These examples demonstrate that ,functional testing can, with fa r less effort than conventional methods, produce test sets that provide complete coverage of SSL faults in practical circuits. Surprisingly, these test sets are also provably of minimal or near-minimal size.
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